This invention relates to a method for forming a titanium polycide gate, and more particularly to a method for forming a titanium polycide gate having a good interface roughness between a titanium silicide layer and a polysilicon layer.
A gate of a MOSFET is comprised of polysilicon or polysilicon/tungsten silicide. As the integrity of the device become high, a line width of the gate is reduced so that it is difficult to lower the resistance in the high integration device having a fine line width with a gate material of polysilicon or polysilicon/tungsten silicide.
So as to obtain the gate having a low resistance in the high integration device, as a gate material, polysilicon/metal silicide which is any one of titanium silicide, cobalt silicide or nikel silicide in stack is used in stead of polysilicon or polysilicon/tungsten silicide. In particular, a concentrative study on titanium silicide is progressed, which comparatively has a characteristic of low resistance, high melting point, easy thin layer formation, easy line patterning and thermal stability required as a gate material.
FIG. 1A to FIG. 1C are sectional views illustrating a method for forming a gate using titanium silicide in the prior art. Referring to FIG. 1A, a semiconductor substrate 1 is prepared and a gate oxide 2 and a doped polysilicon layer 3 are formed over the semiconductor substrate 1 in turn. The doped polysilicon layer 3 is doped with phosphorous ions (P) or arsenic ions (As) in accordance with the conductivity of the channel of the MOSFET. A titanium silicide layer (TiSi.sub.X) 4 of amorphous phase is formed over the doped polysilicon layer 3 with physical vapor deposition PVD.
Referring to FIG. 1B, a heat treatment is carried out to transform the titanium silicide layer 4 of amorphous phase into a titanium silicide layer (TiSi.sub.2) 4a of crystalline phase.
Referring to FIG. 1C, a mask pattern 6 which is comprised of an oxide layer or a nitride layer, is formed over the titanium silicide layer 4a. The titanium silicide 4a, the doped polysilicon 3 and the gate oxide 2 are etched using the mask pattern 6 to form a titanium polycide gate 10 where the polysilicon layer 3 and the titanium silicide layer 4a are in stack.
However, as the following processes are progressed, the characteristic of the titanium polycide gate 10 becomes degraded. For example, as shown in FIG. 2, the titanium polycide gate 10 has a poor interface roughness between the polysilicon layer 3 and the crystalline titanium silicide layer 4a by a heat treatment which is inevitably accompanied in forming a source and drain region and an intermediate insulating layer. Accordingly, the characteristic of the titanium polycide gate 10 becomes deteriorated. It is because titanium of the titanium silicide layer 4a and silicon of the polysilicon layer 3 are reacted. In other word, the polysilicon layer 3 has grain boundaries between grains and a material largely migrates through the grain boundaries rather than grains. Particularly, the polysilicon layer 3 for the titanium polycide gate 10 has a columnar structure having large grains. Accordingly, the material migration through the grain boundaries in the polysilicon layer 3 is relatively larger than that of the polysilicon having a minute grains.
As a result, because the polysilicon layer 3 has a columnar structure, the material migration through the interface between the polysilicon layer 3 and the titanium silicide layer 4a is large so that the interface roughness becomes poor and thus the characteristic of titanium polycide gate 10 is degraded.
Furthermore, when the reaction between the polysilicon layer 3 and the titanium silicide layer 4a is excessive, the titanium silicide layer 4a is contacted with the gate oxide 2 and thus the gate oxide integrity which is a prominent factor becomes degraded.